1. Field of the Invention
The present invention relates generally to non-volatile memories, and in particular to electrically erasable programmable read only memories (i.e., EEPROMs or E.sup.2 PROMs).
2. State of the Art
Read only memories (ROMs) are non-volatile memory devices whose contents are typically programmed during fabrication. Once programmed, a standard ROM cannot be erased and reprogrammed. ROMs find utility in storing information such as operating code, reference data and so forth. Non-volatile ROMs, have the advantage that stored information is not erased when power is removed from the device.
More recently, electrically programmable ROMs (EPROMs) have been developed. EPROMs are memory devices in which data can be written electronically using a technique known as hot electron injection. With hot electron injection, a floating gate is charged by energizing carrier electrons to high energy levels. The high energy electrons are then able to pass through an insulator and into the floating gate.
However, EPROMs typically use ultraviolet (UV) light to erase stored data. Accordingly, erasing an EPROM's contents requires removal of the EPROM from a circuit board. Such a procedure is inconvenient and time consuming.
Electrically erasable PROMs (EEPROM or E.sup.2 PROM) are another variety of known memory devices. A document entitled "Comparison And Trends In Today's Dominant E.sup.2 Technologies", by S. K. Lai, V. K. Dham and D. Guterman generally describes two approaches for charging a floating gate of an E.sup.2 PROM via a thin tunnel oxide.
E.sup.2 PROMs do not require a UV light source for erasure and do not necessarily require the memory device to be removed from the circuit board for reprogramming. Typically, E.sup.2 PROM cells are fabricated using metal oxide semi-conductor field effect transistors (MOSFETs) as described in U.S. Pat. No. 4,477,883. As shown in FIG. 1 of the present application, an E.sup.2 PROM memory cell is formed with a double layer of polysilicon and three electrodes electrically isolated from each other. E.sup.2 PROMs use this configuration to exploit the known phenomenon of electron tunneling during programming and erasure.
Referring to FIG. 1, a first electrode 2 is formed from a first polysilicon layer as a floating gate completely encapsulated in an oxide insulating layer. Typically, the thickness in an area of the oxide under the gate is reduced to form a tunnel window region formed as a thin tunnel oxide layer. This tunnel window region is either defined in the thin gate oxide layer 10 (e.g., 300-400 .ANG.) or a special thicker, decoupling oxide layer (e.g., 3000 .ANG.) of a field shown as field oxide layer 5 in FIG. 1 (e.g., 8500 .ANG.).
During normal operating voltages (e.g., 5 V), the tunnel oxide effectively isolates the floating gate to prevent charge migration to or from the floating gate. However, when subjected to relatively high voltages (e.g., 20 V), electrons tunnel through the thin oxide insulating layer in the aforementioned tunnel window region. Thus, a high voltage state can be used to program or erase the floating gate. When the floating polysilicon is charged positive, the memory cell will be turned on and conduct a current during a read operation. When the floating polysilicon is charged negative, the memory cell is turned off and will not conduct current during a read operation.
As shown in FIG. 1, a second electrode 4 is formed from an n- implant in a substrate 1 as a tunneling gate. Electrons tunnel between the electrodes 2 and 4 via the thin tunnel oxide layer 6 (e.g., 100 .ANG.) formed within a tunnel window region of the decoupling oxide layer 7 interposed between the electrodes 2 and 4. A third electrode 8 is formed from a second polysilicon layer as a coupling gate.
The tunneling gate 4 is capacitively coupled to the floating gate 2 as is the coupling gate 8. The combination of the coupling gate 8, the floating gate 2 and the tunneling gate 4 can thus be represented schematically by two capacitors connected in series. The tunneling gate 4 and the coupling gate 8 control the charge and discharge (programming and erasure) of majority carriers (i.e., electrons) in the floating gate 2.
As shown in FIG. 1, a select transistor 12 is formed on substrate 1. The select transistor is formed with a portion of the tunneling gate 4, an n- implant representing a gate select contact 14, a portion of the thin gate oxide layer 10 and portion 16 of the first polysilicon layer.
When data is written into the FIG. 1 memory cell, a low voltage (e.g., ground) is supplied via the select transistors (e.g., via gate select contact 14) to the tunneling gate 4. In addition, the coupling gate 8 is placed at a high potential (e.g., 20 volts). Accordingly, electrons pass from the gate select contact 14 across the substrate 1 to the tunneling gate 4. From the tunneling gate 4, these electrons pass through the thin tunnel oxide layer 6 and into the floating gate 2 where a negative charge is stored. The tunneling current flows through the thin tunnel oxide layer 6 in a region where the tunneling gate 4 and the floating gate 2 overlap. Electrons are thereby injected into the floating gate 2 to write the logic low, or ".phi.". In this state, there is no current flow through this cell during a read operation.
To write a logic level 1, the coupling gate 8 associated with the floating gate 2 is grounded while the gate select contact 14 and the tunneling gate 4 are raised to a high potential (e.g., 20 volts). As a result, the floating gate 2 returns to a logic level high, or "1" by emitting tunneling electrons to the voltage source via the thin oxide layer 6. The floating gate is thereby left positively charged and the cell conducts a current during a read operation. In alternate embodiments, polysilicon-to-polysilicon tunneling can be used to remove floating gate electrons from the floating gate during an erasure mode.
FIGS. 2a-2d show a method for fabricating a memory cell of an E.sup.2 PROM such as that shown in FIG. 1. FIG. 2a shows formation of the FIG. 1 E.sup.2 PROM cell from a point following coating of a photoresist layer 17 on the field oxide layer 5 and substrate 1. A window in the photoresist layer 17, generally represented as window 18 encompasses a portion of the field oxide layer 5 and the thin gate oxide layer 10 so that an arsenic (As) implant can be used to form the tunneling gate 4 of FIG. 1. A thicker decoupling oxide 7 is then grown over the arsenic implanted area.
FIG. 2b shows the arsenic implanted as the tunneling gate 4. As shown in FIG. 2b, the field oxide layer 5 is approximately 8500 Angstroms (.ANG.) and the decoupling oxide layer 7 is shown to be approximately 3000 .ANG..
In FIG. 2c, a tunneling window 20 is formed in the decoupling oxide layer 7 following coating of a photoresist layer 22 and an etching process. The etching process is used to remove a portion of the decoupling oxide layer 7 located within the tunnel window 20. This portion of the decoupling oxide layer is removed down to the substrate 1.
In FIG. 2d, the photoresist layer 22 has been stripped and a tunnel window oxide layer 6, approximately 100 .ANG. thick, is grown. Afterwards, the first polysilicon layer 2 is deposited and formation of the remaining portion of the FIG. 1 E.sup.2 PROM continued in known fashion.
The foregoing fabrication process of the FIG. 1 E.sup.2 PROM has several, significant drawbacks. For example, the FIG. 2c etching process has significant disadvantages. Generally speaking, there are two types of etching: dry etching using plasma to etch a surface, and wet etching where a liquid chemical is used to dissolve material on a wafer surface.
The use of a dry etch to perform the etching process of FIG. 2c can significantly damage the silicon surface during removal of the decoupling oxide down to the substrate 1. This degrades the quality of the tunnel oxide layer grown in the tunnel area. On the other hand, a wet etch process is difficult to control through the thick decoupling oxide layer 7. For example, the etching chemical may not wet the entire area within the tunnel window 20 such that an incomplete etching process may occur and significantly degrade the quality of the tunnel window oxide layer. Additionally, the wet chemical may not wet all the tunnel windows on an IC chip (which can number many thousand) leaving some windows unetched or partially etched and resulting in bad memory cells and low net yield.
Alternately, the chemical used for the wet etch may over-etch the area within the tunnel window 20, similarly degrading performance of the tunnel window oxide layer by increasing its size and the potential for current leakage during operation. This increase in tunnel window size also affects the electrical capacitance of the tunnel oxide which adversely affects the electrical performance. Finally, the wetting efficiency of a liquid is dependent on the size of the hole being wetted; it becomes more difficult as the hole size is reduced. This makes wet etching of the tunnel window less dependable as transistor sizes decrease and IC density increases.
Because the FIG. 2a-2d process uses a single n- implant for the tunneling gate 4, design flexibility of the tunneling gate is also limited. Certain performance characteristics must be compromised to optimize other properties of the tunneling gate. For example, it is known that if the substrate 4 is very heavily doped or implanted, the quality of the oxide grown (i.e., tunnel oxide 6) is compromised, resulting in higher leakage through the tunnel oxide layer 6. Because a single implant is used to create the tunneling gate 4, the dose of the entire region must be sufficiently low to prevent leakage current across the tunnel oxide layer 6 during normal operation. However, this low dosage results in a high resistance tunneling gate which hinders electron movement in and out of the tunneling gate via the gate select contact 14, thus decreasing operating efficiency during programming and erasure.
Accordingly, it would be desirable to provide a semiconductor memory device and method for fabricating a semiconductor memory device which overcomes the aforementioned deficiencies.